Intel disclosed a bit more about its current Ivy Bridge chips and upcoming Xeon Phi (Knights Corner) many-integrated-core design. Almost all of these talks divulged architectural details of the chips, but did not give details of the specific products. Mark Papermaster, the company's senior VP and CTO, spoke in his keynote about the "Surround Computing" era with ubiquitous computing supporting consistent computing experiences across a wide range of devices, all connected to the cloud. As the company has before, he stressed the benefits of heterogeneous system architecture and accelerated processing units (APUs), AMD's name for chips that combine CPUs and GPU capability.

The upcoming Steamroller design seems to fix some bottlenecks in the company's existing Bulldozer architecture, in which two integer cores share a single floating point unit and other components. The changes are meant to "feed the cores faster" to improve the single-core performance. Among other things, the cores will still share a single fetch unit, but each integer core will now get its own decode module and an increased instruction cache size. Overall, he said, this will result in a 30 percent improvement in operations per clock cycle.

The floating point unit has also been "rebalanced" and streamlined and the level 2 cache now supports dynamic resizing. AMD Steamroller core diagram Papermaster also discussed the company's Freedom Fabric technology, an off-chip interconnect fabric developed by SeaMicro, which AMD recently purchased. He said this will allow system makers to create systems with hundreds, and eventually thousands, of SoC modules. This can significantly improve the total cost of ownership in certain applications. AMD Freedom Fabric Overall, he concluded, "The pure speeds and feeds race is over. It's about the solution."